1. Field of the Invention
The present invention relates to electronic devices, and in particular, to circuits relating to different supply voltage levels.
2. Description of Related Art
With microprocessor designs, there often is a need to use separate power supplies for microprocessor input-output (I/O) circuits and microprocessor core circuits. In a microprocessor system power and thermal management techniques for the core require changing the power supply voltages during use. While core clock frequencies are scaled back when supply voltage is reduced to save power, the I/O circuitry operates at a fixed system clock frequency. It is difficult to meet system timing requirements if the I/O supply has to function at the lowest values supported by the core supply. Also, the microprocessor's I/O circuitry interfaces over one or more buses with other devices which may have I/O modules fabricated using older manufacturing processes. Hence, such I/O modules do not function well at the lowest supply settings for the microprocessor core.
Having separate power supplies for the core and I/O sections of the microprocessor requires the use of level shifters. Level shifters propagate signals between supply domains while maintaining full rail swings between supply and ground. Without full-rail output swings, a signal would be more sensitive to noise and a following stage logic gate could dissipate large amounts of power by passing DC current between supply and ground. Level shifters are used to address this issue. While level shifters have the desirable attribute of rail-to-rail output swings, they exhibit longer gate delays than standard CMOS logic and are prone to significant delay variation due to changes in process, temperature, and the two supply voltages.
In source-synchronous system interfaces between microprocessors and buses connected to other devices, it is necessary in the microprocessor to use level shifters for transitioning on-chip signals between different supply voltage domains (also simply referred to as supply domains) for the core and I/O circuits. Hence, this provides one example of where level shifters introduce extra timing skew, in this case between the rising and falling edges or transitions of the data signals and strobes (forwarded clock signals). For a source-synchronous bus, an important metric is the relative timing between data and strobe edges (signal transitions). When subject to variations, the data and strobe transitioning in the same direction track each other well. The worst case timing skew occurs when data and strobe are transitioning in opposite directions.
Referring to FIG. 1, there is illustrated a prior art converter circuit, which includes a single level shifter 10 in the data path extending between a core supply domain 12 and a I/O supply domain 14. The two domains 12 and 14 are separated by a dashed line 16. A master latch 18 and slave latch 20 receives a Data1 signal which, in response to a clock signal, is provided to the level shifter 10 as a Data2 signal. The level shifter 10 produces a Level Shifted Data signal as an output. With this topology, the variation in the timing of a single edge may be significant, but the difference in the timing of rising and falling signals shows even more variation.
Referring to FIG. 2, the Clock, Data2 and Level Shifted Data signals are shown for the converter circuit of FIG. 1. The Data2 signal, relative to the rising edge of the Clock signal, is delayed based upon the delay introduced by the master and slave latches 18 and 20. Thereafter, the Level Shifted Data signal is further delayed by the level shifter 10, but more importantly, the cross hatching in the Level Shifted Data signal represents the miss-match in rise and fall delays of the rising and falling edges of the Level Shifted Data signal. This timing skew is sometimes referred to as Tco skew.